The present application relates to semiconductor devices and methods of forming the same. More particularly, the present application relates to finFET devices including epitaxial semiconductor material portions which have a non-planar bottom surface and a non-planar top surface which merge adjacent exposed semiconductor fin portions and methods of forming the same.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties.
One setback facing CMOS transistor scaling is the ability to control transistor leakage current (Ioff), while increasing drive current (Ion). Fully depleted devices such as, for example, extremely thin semiconductor on insulator (ETSOI), Trigate and finFET having sub-threshold voltage slope approaching theoretical values of 60 mV/dec, may be a good candidate since these devices offer excellent short channel effect (SCE) control. However, it is known that these devices greatly suffer high extension resistance which can degrade the transistor performance. Moreover, traditional ion implantation in such devices results in high resistance due to amorphization of small silicon fins in which little or no silicon seeds are available for recrystallization from activation anneal.